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Design of 4 Bit Binary Counter using Behavior Modeling Style (Verilog CODE) - Design of 4 Bit Binary Counter using Behavior Modeling Style - Output Waveform: 4 Bit Binary Counter Verilog CODE. Design of 4 Bit Comparator using Behavior Modeling Style (Verilog CODE). Verilog example codes with TestBench code along with the link to example code in EDA Playground. 4-bit Asynchronous Counter; Adders; 8-bit Carry ripple adder; 8-bit Carry Look-Ahead adder; 8-bit Carry skip adder; 4-bit BCD adder and Subs-tractor; Multipliers; 4x4 Unsigned array Multiplier.
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I'm trying to design a 4-bit counter with T-flipflop, here's what i did:
1- From a D-flipflop to T-flipflop:
with RTL shematic :
following this 'D_ff to T_ff' conversion:
2- Then, i instantiated 4 T-flipflops in the top module and connected the output of each flipflop to the
clk
of the next one:with RTL schematic :
to follow this diagram:
![Code Code](http://3.bp.blogspot.com/_c99lLjgQ8ho/TI3Pp2skf_I/AAAAAAAAAp4/yFGBDtXQbKA/s1600/john_ckt.bmp)
We know that T-flipflop is just a JK-flipflop with J and K connected to each other and that's what we have here, so consider them as T-flipflops.
3-The simulation:
4- Finally, my questions:
1) why
Q1
is the ONLY output that operates properly?2) Why
Q2
, Q3
, Q4
starts with 1
although i have initialized them as 0
?I can't figure out what's missing, i tried to play around but nothing worked and i'm stuck here!
Edit: my testbench:
Mohamed Sayed
Mohamed SayedMohamed Sayed
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Active6 years, 7 months ago
I wrote this code for simulating an asynchronous counter using D flip flop. The program gives correct output for the first to iterations but then the output doesn't change at all. What am I doing wrong?
Here is the code:
1st module:
second module:
3rd module:
Morgan16.4k55 gold badges4747 silver badges7272 bronze badges
James AflredJames Aflred4722 gold badges55 silver badges1111 bronze badges
2 Answers
Looking at this picture of a ripple counter, the only input from your testharness should be the clock.
The type of flop used would typically look something like:
In module 1
always@(posedge clk ..
you should be using non-blocking <=
assignments instead of =
.In module 3 you have an always block with out a sensitivity list, I would add the
@*
, This looks like you really want an initial with a repeat or a for loop to execute your test then call $finish()
once complete. I have used #5ns
SystemVerilog below but you could change to #5
if required.Trying out your example, this is what I have ended up with I think it is what you were trying to do: NOTE the correct answer is
~out
.Module 1, could be expanded with q and q_bar outputs.
Module 2
Module 3 (Testharness)
MorganMorgan16.4k55 gold badges4747 silver badges7272 bronze badges
I'm not sure what you expect your output to do, but one problem is that you are always resetting your DFFs.
toolictoolic35.7k44 gold badges5050 silver badges8181 bronze badges
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